Component PCB and Package Design Engineer

Ferric is a technology startup based in New York City that is pioneering an entirely new approach to power delivery for Integrated Circuits and Electronic Assemblies. This approach leverages Ferric’s integration of thin-film magnetic inductors with CMOS technology to enable a significant improvement in the integration density and efficiency of voltage regulators (VRs) compared with current commercially available technologies.

As a Component PCB and Package Design Engineer, you will gain exposure to the full product-life of Ferric’s ICs by working with a diverse cross-functional team including IC designers, test & application engineers, component designers, engineering vendors, the fab, and our customers. Your primary responsibilities will be designing and simulating discrete circuit components and integrating them in a full system PCB. This position requires a background in component analysis, PCB layout best practices and experience in transitioning from simulation software to physical designs. Applicants should be self-motivated and willing to take full responsibility for finding engineering solutions. They must have excellent problem-solving and analytical skills, as well as excellent oral and written communication skills to work well and contribute to a team.

Primary Responsibilities:

  • Schematic and layout design for PCBs used for the validation, evaluation, and/or demonstration for Ferric’s products

  • Layout design for organic package substrates or HDI substrate or IC substrate used for the for Ferric’s products

  • Extracting and modeling of PCB Power Delivery Networks (PDN) and Clock Routing for estimation of parasitic effects

  • Support design engineers to simulate and modeling of magnetic devices such as transformers and inductors for circuit level simulations 

  • Designing and selecting components for PCBs in power conversion applications and device measurements

  • Working with circuit design teams for full system analysis in the inclusion of the aforementioned extractions

  • Collaborate with Ferric’s circuit, test, and applications teams to ensure that PCB and package designs meet requirements  

  • Bench-level verification of PCB / package performance

  • Analyzing RF performance of various physical components

  • Developing, maintaining, and executing MATLAB and Python scripts to analyze device performance and automation of FEA simulations

  • Generating compact models of our devices for simulation in Cadence Spectre

Desired Skills and Experience:

  • Education:  Bachelor’s or Master’s Degree in EE

  • Industry Experience: 1-5 years

  • Experience with PCB design and assembly, including component selection, soldering, etc.

  • Strong Understanding of PCB and package substrate parasitics and PDN extraction 

  • Knowledge of magnetic concepts and design, such as reluctance circuitry, magnetic losses and magnetic saturation

  • Knowledge of DC-DC power converters/regulators (Buck, Boost, Buck-Boost, LDO, etc.)

  • Understanding of s-parameter analysis, de-embedding techniques and conversion between RF parameters

  • Programming Languages:  Python, MATLAB

  • Lab experience with the following equipment: Oscilloscope, Digital Multimeter (DMM), Spectrum Analyzer, Vector Network Analyzer (VNA)

  • Software: Cadence Allegro Package Designer, Cadence Virtuoso Suite, Cadence Spectre, HSPICE, HFSS, SIwave, Xilinx ISE, and Linux

Desired Characteristics & Attributes::

  • Passionate, self-starter with strong commitment to flawless execution

  • Excellent written and verbal communication skills required

  • Ability to work well with others in a fast-paced collaborative team environment 

Location: New York, NY 

Eligibility: Applicant must currently be eligible to work for any employer in the US. Visa sponsorship is not available for this position.

Compensation: Base salary range for this position $80k-115k with additional equity and benefits


To apply please email your resume to careers@ferricsemi.com. Ferric is unable to provide sponsorship for employment visa status for this position.